`timescale 1ns/10ps
`define clock_period 20

module counter_8bit_tb;

	reg clk;
	reg rst_n;
	reg cin;
	reg load;
	reg [7:0] data;
	
	wire [7:0] count;
	wire out;

	counter_8bit counter0(
		.Clk(clk),
		.Rst_n(rst_n),
		.Cin(cin),
		.Data(data),
		.Load(load),
		.Count(count),
		.Out(out)
	);

	
	always #(`clock_period / 2) clk = ~clk; //周期时钟信号
	
	//测试过程
	initial begin
		//初始化信号
		clk = 1'b0;
		rst_n = 1'b0;
		cin = 1'b0;
		load = 1'b0;
		data = 8'b1000_0000;
		
		rst_n = 1'b0;
		#(`clock_period * 2);
		rst_n = 1'b1;//复位信号
		
		#(`clock_period * 10);//让仿真运行一段时间，观察输出
		
		//有输入进位的计数情况
		cin = 1'b1;
		#(`clock_period);
		cin = 1'b0;
		
		#(`clock_period * 10);
		
		load = 1'b1;
		#(`clock_period);
		load = 1'b0;
		
		#(`clock_period * 10);
		
		$stop;
	end
	
endmodule
	